b1fbfaaacc
Although `keychron/c2_pro/ansi/rgb` and `keychron/c2_pro/ansi/white` use the same custom matrix code, the matrix layouts are slightly different; in particular, only the `keychron/c2_pro/ansi/white` board actually uses column 19. However, the handling of column 19 in the custom matrix code was broken, therefore that column did not work. Looks like the custom matrix code assumes that `SHIFT_COL_END` refers to the last column connected to the shift register, and not to the column past that; so the value of `SHIFT_COL_END` needs to be changed from 19 to 18 (columns 11...18 are connected to the shift register, and column 19 is connected to the C14 pin). Also the code which was determining `SIZE_T` and `UNSELECT_ALL_COL` had an off-by-one bug when counting the required number of bits (again due to the confusion on the `SHIFT_COL_END` meaning); this had been fixed too (the actual behavior of that part of the code did not change, because both the old and the new version select the 8 bit variant).
44 lines
1.4 KiB
C
44 lines
1.4 KiB
C
/* Copyright 2023 @ Keychron(https://www.keychron.com)
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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/* DIP switch */
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#define DIP_SWITCH_MATRIX_GRID { { 5, 4 } }
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/* Disable DIP switch in matrix data */
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#define MATRIX_MASKED
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/* EEPROM Driver Configuration */
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#define WEAR_LEVELING_LOGICAL_SIZE 2048
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#define WEAR_LEVELING_BACKING_SIZE (WEAR_LEVELING_LOGICAL_SIZE * 2)
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/* Increase I2C speed to 1000 KHz */
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#define I2C1_TIMINGR_PRESC 0U
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#define I2C1_TIMINGR_SCLDEL 3U
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#define I2C1_TIMINGR_SDADEL 0U
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#define I2C1_TIMINGR_SCLH 15U
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#define I2C1_TIMINGR_SCLL 51U
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/* Old default behavior of mod-taps */
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#define HOLD_ON_OTHER_KEY_PRESS
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/* HC595 used pins definiton */
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#define HC595_STCP A0
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#define HC595_SHCP A1
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#define HC595_DS C15
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#define SHIFT_COL_START 11
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#define SHIFT_COL_END 18
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